Parallel Layer-Aware Partitioning for 3D Designs

As compared to two-dimensional (2D) ICs, 3D integration is a breakthrough technology of growing importance that has the potential to offer significant performance and functional benefits. This emerging technology allows stacking multiple layers of dies and resolves the vertical connection issue by through-silicon vias (TSVs). However, though a TSV is considered a good solution for vertical connection, it also occupies significant silicon estate and incurs reliability problem. Because of these challenges, minimizing the number of TSVs becomes an important design issue. Therefore, in this paper, we propose a two-phased parallel layer-aware partitioning algorithm for TSV minimization in 3D structures. In the first phase, we employ OpenMP to parallelize the 2-way min-cut partitioning and get the initial solution. In the second phase, we further improve the result using a parallel simulated annealing approach on GPU. Experimental results show that the proposed algorithm can reduce the number of TSVs by about 39% as compared to several existing methods.